1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which is suitable when it is applied to a semiconductor device including a majority carrier device such as an MOS transistor which is used in various kinds of electronic apparatuses or to a highly integrated semiconductor device of a high speed and a high withstanding voltage.
2. Related Background Art
In a conventional bipolar transistor, there is a limitation in the high frequency characteristics due to an Early effect, a withstanding voltage, or a parasitic capacitance which depends on the design of the base region.
For instance, in case of a lateral type pnp bipolar transistor shown in FIG. 1, an extent of a current and a substantially wide space region are necessary in terms of a structure, so that a current amplification factor is low. Since a depletion layer from a collector region 101 extends to a base region 103, it is necessary to set a thickness of base layer (n-Epi) 104 to a large value because of an Early effect or a junction withstanding voltage. There is a problem such that good high frequency characteristics cannot be obtained. Since the base region 103 is large, there is also a problem such that a parasitic capacitance of the base region 103 is large. In particular, when the base also has a buried region, a capacitance between the base and a p-type substrate 105 is large and the high frequency characteristics deteriorate. In FIG. 1, reference numeral 106 denotes an n.sup.+ region; 107 an insulative layer such as SiO.sub.2 or the like; 108 a channel stop; and 109 a contact region.
A lateral type bipolar transistor with a gate shown in FIGS. 2A to 2C also has a similar drawback and a problem on process. In the diagram, FIG. 2A is a plan view, FIG. 2B is a cross sectional view taken along the line A--A' in FIG. 2A, and FIG. 2C is a cross sectional view taken along the line B--B' in FIG. 2A. Namely, n.sup.+ polysilicon 205 is used as a gate 201, the surface potential between an emitter 203 and a collector 202 is reduced, and a mutual conductance (C.sub.m) is raised. In the n.sup.+ polysilicon 205, no ohmic contact is obtained for a p-well 204. As shown by .alpha. in FIG. 2B, there is a problem such that after completion of the working, an ohmic contact must be obtained by a metal 206 through the p-well 204 and an ohmic contact region 207.
On the other hand, a Bi-CMOS semiconductor device in which a bipolar transistor and a CMOS transistor mixedly exist is promising and has widely been put into practical use as a semiconductor device having advantages of both of those transistors: namely, a high processing speed, a high driving ability, and a high analog precision of the bipolar transistor; and a high packing performance, a low electric power consumption, a high input impedance, and the like of the CMOS transistor.
In the conventional Bi-CMOS process, a bipolar transistor and a CMOS transistor are formed by different processes, respectively. FIG. 3 is a flowchart for a conventional typical Bi-CMOS process. In the conventional examples, the case of forming a bipolar transistor of an ion implantation emitter and the case of forming a bipolar transistor of a polysilicon emitter are shown, respectively.
As will be understood from FIG. 3, a conventional Bi-CMOS has a problem such that its manufacturing process is complicated. Namely, in case of forming a bipolar transistor of an ion implantation emitter, four masks are added to the standard CMOS process. In case of forming a bipolar transistor of a polysilicon emitter, six masks are added to the standard CMOS process. Consequently, 14 masks and 16 masks are necessary through the Bi-CMOS process, respectively. According to the conventional Bi-CMOS process, an occupied area of a bipolar transistor region and an element isolation area are large, such large areas obstruct the realization of a high integration degree.
As a method of solving such a problem, for example, a trial such as to form a bipolar transistor without adding the masks in the CMOS processing step has been performed as shown in "IEEE Transactions On Electron Devices", Vol. 38 , No. 11 , pages 2487-2496, 1991. FIGS. 4A to 4C show a lateral type npn bipolar transistor which is formed on a bulk silicon wafer by the above method. In the diagram, when n.sup.+ polysilicon 401 is patterned, a channel contact region 402 is opened. In order to obtain an ohmic contact with a p well 404, a p.sup.+ region 406 is ion implanted into the opening portion 402 by the same step as a step of forming a source and a drain of a PMOS transistor. Further, a metal contact region 403 which is wider than an opening of a channel contact is opened. A channel potential is obtained by a metal (not shown) deposited in such an opening portion, thereby forming a base electrode. FIG. 4A is a schematic plan view. FIG. 4B is a schematic cross sectional view taken along the line A--A' in FIG. 4A.
The lateral type bipolar transistor formed on the bulk silicon by the above method has a problem that it is difficult to not only improve the driving ability but also maintain the withstanding voltage. That is, in order to raise a current amplification factor and a high frequency cut-off frequency, it is necessary to reduce a gate length of polysilicon serving as a base width and to decrease a concentration of the p well serving as a base region. However, since a punch through withstanding voltage between the emitter and the collector decreases due to this, it is necessary to increase the polysilicon gate length or to reduce a power source voltage on the collector side. However, in such a bipolar transistor of a long base width and a low collector voltage, it cannot help deteriorating the driving ability.
Such a lateral type bipolar transistor formed on the bulk silicon has a problem that a high processing speed is obstructed. This is because the base region is a large p well region and a junction capacity between the base and the p well substrate is mainly added as a parasitic capacity to the base.
In the conventional silicon wafer bulk process, on the other hand, a vertical type bipolar transistor and a lateral type transistor are formed as shown in FIGS. 5 and 6, respectively. In FIG. 5, reference numeral 251 denotes a first vertical type npn bipolar transistor; 252 a second vertical type npn bipolar transistor; and 253 an element isolation region to electrically isolate the bipolar transistors 251 and 252. In the diagram, a collector of the bipolar transistor 251 and an emitter of the bipolar transistor 252 are electrically connected by a wiring 265. Reference numeral 254 denotes a p-type silicon substrate; 255 and 255' n.sup.+ -type regions serving as collector regions of the bipolar transistors; 256 an n.sup.- -type epitaxial region; 257 a p-type region to electrically isolate the bipolar transistors 251 and 252; 258 a selective oxide region; 259 and 259' collector lead-out layers; 260 and 260' p-type base regions; 261 and 261' n.sup.+ type emitter regions; 262 an inter-layer insulative layer; 263, 264, 265, 266, and 267 Al electrodes; and 268 a passivation insulative layer.
In FIG. 6, reference numeral 271 denotes a first lateral type pnp bipolar transistor; 272 a second lateral type pnp bipolar transistor; and 273 an element isolation region to electrically isolate the bipolar transistors 271 and 272. In the diagram, a collector of the bipolar transistor 271 and an emitter of the bipolar transistor 272 are electrically connected by a wiring 285. Reference numeral 274 denotes a p-type silicon substrate; 275 and 275' n.sup.+ -type regions serving as base regions of the bipolar transistors; 276 an n.sup.- -type epitaxial region; 277 a p-type region to electrically isolate the bipolar transistors 271 and 272; 278 a selective oxide region; 279 and 279' base lead-out layers; 280 and 280' p.sup.+ -type emitter regions; 281 and 281' p.sup.+ -type collector regions; 282 an inter-layer insulative layer; 283, 284, 285, 286, and 287 Al electrodes; and 288 a passivation insulative layer.
The above bipolar transistors of the bulk vertical and lateral types need the element isolation regions each for electrically isolating the adjacent bipolar transistors, so that there is a problem such that a high integration degree cannot be obtained.
Each of the above bipolar transistors of the bulk vertical and lateral types needs the contact and wiring for connecting the collectors or emitters of the adjacent bipolar transistors or for connecting the collector of one of the adjacent bipolar transistors and the emitter of the other bipolar transistor. There is, consequently, a problem such that a contact resistance, a wiring resistance, and a wiring capacity become loads and the operating speed of the transistor is limited.